1. Field of the Invention
The present disclosure generally relates to the fabrication of semiconductor devices, and, more particularly, to a finFET device including a silicon oxycarbon (SiOC) isolation structure and methods for making same.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided on a restricted chip area. Transistors come in a variety of shapes and forms, e.g., planar transistors, FinFET transistors, nanowire devices, etc. The transistors are typically either NMOS (NFET) or PMOS (PFET) type devices wherein the “N” and “P” designation is based upon the type of dopants used to create the source/drain regions of the devices. So-called CMOS (Complementary Metal Oxide Semiconductor) technology or products refers to integrated circuit products that are manufactured using both NMOS and PMOS transistor devices. Irrespective of the physical configuration of the transistor device, each device comprises drain and source regions and a gate electrode structure positioned above and between the source/drain regions. Upon application of an appropriate control voltage to the gate electrode, a conductive channel region forms between the drain region and the source region.
In some applications, fins for FinFET devices are formed such that the fin is vertically spaced apart from and above the substrate with an isolation material positioned between the fin and the substrate. FIG. 1 is a perspective view of an illustrative prior art FinFET semiconductor device 100 that is formed above a semiconductor substrate 105 at an intermediate point during fabrication. In this example, the FinFET device 100 includes three illustrative fins 110, an isolation structure 130, a gate structure 115, sidewall spacers 120 and a gate cap layer 125. The fins 110 have a three-dimensional configuration: a height, a width, and an axial length. The portions of the fins 110 covered by the gate structure 115 are the channel regions of the FinFET device 100, while the portions of the fins 110 positioned laterally outside of the spacers 120 are part of the source/drain regions of the device 100. Although not depicted, the portions of the fins 110 in the source/drain regions may have additional epi semiconductor material formed thereon in either a merged or unmerged condition.
One technique for forming the isolation structure 130 includes forming a first oxide layer using a flowable chemical vapor deposition (FCVD) process to fill the gaps between the fins 110, performing an annealing process to densify the first oxide layer, and forming a second oxide layer (e.g., tetraethyl orthosilicate (TEOS)) (not separately shown) above the densified first oxide layer. Subsequently, a planarization process is performed to expose a cap layer (not shown) disposed above the fins 110 and a wet etch process is performed to recess the remaining oxide to create the isolation structure 130 illustrated in FIG. 1.
The annealing process to densify the first oxide layer increases the thermal budget and may also create inherent stress in the structure, leading to an undesirable bending of the vertical axis of the fins 110. The planarization process also introduces variations that depend on the pitch between the fins 110. Regions with increased pitch experience increased dishing of the second oxide layer relative to regions with increased pitch. As a result, the height of the isolation structure 130 may vary after the wet etch across the different regions of the substrate, causing an associated variation in fin height.
The present disclosure is directed to various methods of forming isolation structures on FinFET devices and resulting devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.